1. Field of the Invention
The present invention generally relates to the field of memory devices with recesses gate structures, and more particularly to a memory cell with a halogen-doped dielectric layer and a fabrication method thereof.
2. Description of the Prior Art
For years the trend in the memory industry as well as the semiconductor industry has been to scale down the size of memory cells in order to increase the integration level and thus the memory capacity of DRAM chips. In a DRAM cell with a recessed gate, the current leakage caused by a capacitor is often reduced or avoided thanks to a relatively long channel length beneath the recessed gate. Therefore, more and more DRAM cells are equipped with recessed gates rather than with a conventional planar gate structure due to their superior performances.
In general, the DRAM cells with a recessed gate include a transistor device and a charge storage device. More precisely, the transistor device includes a pair of source/drain regions, a recessed gate and a carrier channel inside a semiconductor substrate. The charge storage device is often a capacitor used to store charges. During the operation of the DRAM cell, a bias voltage is applied to the gate electrode inside the recessed gate, which enables charges to flow along the carrier channel between the source/drain regions. The charges flow in and are stored in the corresponding capacitor. However, due to limitations in fabrication technologies, many defects are formed in the gate dielectric layer on the bottom of the recessed gate. More precisely, these defects are caused by dangling bonds being located on the surface of the oxide layer and/or at oxide layer/semiconductor substrate interface. Under these conditions, several current paths are created by these defects, leading charges to be released from the capacitor unusually, which is obviously bad for the data retention time of the DRAM device.
Therefore, there is still a need to provide an improved memory cell with a recessed gate and a fabrication method thereof that reduces the defects caused by dangling bonds and enhances the performance and reliability of the corresponding memory device.